Currently, researches on the S/D engineering include the ultra shallow low resistance PN junction S/D technology, the low schottky barrier metal S/D technology, the elevated S/D technology, etc.
The ultra shallow low resistance PN junction S/D technology has a very high processing requirement. It requires a low energy ion implantation to implement the ultra shallow low resistance S/D, and bears a high temperature annealing of about 1000° C. to activate the doped ions. The annealing process under a high temperature not only affects reliabilities of the high k gate dielectric layer and the metal gate, but also easily causes problems such as source and drain breakthrough due to ion diffusion.
On the other hand, for the low schottky barrier metal S/D technology, it is also a great challenge to decrease the schottky barrier height while reducing the S/D resistance. Currently, the common method is to deposit a metal layer (e.g., Ni and NiPt alloy) on a semiconductor substrate at the S/D, and through an annealing process, make the metal layer react with the semiconductor substrate to generate a metal silicide (e.g., NiSi, NiPtSi, etc.). On this basis, the schottky barrier is controlled by way of ion implantation and impurity segregation methods. The methods requires refined process conditions, which proposes high requirements of parameters such as thickness, annealing time and temperature of the deposited metal, and the diffusion control of the metal in the channel direction. In addition, reduction of the S/D parasitic resistance in the low schottky barrier S/D technology is also a challenge urgently to be solved.
For the elevated S/D technology, main process is to firstly form a gate structure on the semiconductor substrate, then perform a light doped ion implantation on the semiconductor substrate at the S/D, and form an insulation layer sidewall at both sides of the gate. Based on this structure, an elevated S/D layer (e.g., GeSi, SiC, etc.) is formed on the S/D by way of an epitaxial growth. Another preparing method of the elevated S/D process is to embeddedly introduce semiconductor silicide or carbide (e.g., GeSi, SiC, etc.) by way of an epitaxial growth in the S/D region during a gate last process. Although the above elevated S/D technology in a certain extent reduces the S/D resistance and increases the stress, the device structure and the preparing process still need to be optimized due to problems such as the inherent doping density limitation and the contact resistance, so as to further reduce the S/D parasitic resistance and optimize the mobility caused by the device structure and the process.